Memory system and method of controlling nonvolatile memory

ABSTRACT

A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory stores data encoded by using an error correcting code for correcting n-bit errors(n is an integer of 3 or more) or less. The memory controller reads a received word from the nonvolatile memory, calculates a syndrome by using the read received word, estimates the number of bit errors by using the syndrome. When the number of bit errors is 2 or 3, the memory controller calculates an inverse element of a value calculated based on the syndrome, executes, by using the inverse element, variable transformation on a variable of an error locator polynomial corresponding to the number of bit errors and calculation of a root of a transformed polynomial obtained by transforming the error locator polynomial according to the variable transformation, executes variable inverse transformation on the root of the transformed polynomial to obtain the root of the error locator polynomial, and corrects the error in the error location corresponding to the root of the error locator polynomial.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2022-086172, filed on May 26, 2022; theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a memory system and acontrol method.

BACKGROUND

In order to protect data to be stored, a memory system generally storesdata encoded by using error correcting codes. Therefore, the data storedin the memory system is read as a received word and decoding isperformed on the read data which has been encoded by using errorcorrecting codes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a memory system according to an embodiment;

FIG. 2 is a block diagram of a decoder according to the embodiment;

FIG. 3 is a diagram illustrating a configuration example of a circuit ofa comparative example;

FIG. 4 is a flowchart of decoding processing according to theembodiment;

FIG. 5 is a diagram illustrating a configuration example of a rootcalculation circuit according to the first modification;

FIG. 6 is a diagram illustrating a configuration example of a rootcalculation circuit according to the second modification; and

FIG. 7 is a diagram illustrating a configuration example of a rootcalculation circuit according to the third modification.

DETAILED DESCRIPTION

A memory system according to an embodiment includes a nonvolatile memoryand a memory controller. The nonvolatile memory stores data encoded byusing an error correcting code for correcting n-bit errors (n is aninteger of 3 or more) or less. The memory controller reads a receivedword from the nonvolatile memory, calculates a syndrome by using theread received word, estimates the number of bit errors by using thesyndrome. When the number of bit errors is 2 or 3, the memory controllercalculates an inverse element of a value calculated based on thesyndrome, executes, by using the inverse element, variabletransformation on a variable of an error locator polynomialcorresponding to the number of bit errors and calculation of a root of atransformed polynomial obtained by transforming the error locatorpolynomial according to the variable transformation, executes variableinverse transformation on the root of the transformed polynomial toobtain the root of the error locator polynomial, and corrects the errorin the error location corresponding to the root of the error locatorpolynomial.

Hereinafter, a preferred embodiment of the memory system according tothe present invention will be described in detail with reference to theaccompanying drawings.

First, a memory system according to the present embodiment will bedescribed in detail with reference to the drawings. FIG. 1 is a blockdiagram illustrating a schematic configuration example of a memorysystem according to the present embodiment. As illustrated in FIG. 1 , amemory system 1 includes a memory controller 10 and a nonvolatile memory20. The memory system 1 can be connected to a host 30 and is illustratedin a state connected to the host 30, in FIG. 1 . The host 30 may be anelectronic device such as a personal computer or a mobile terminal.

The nonvolatile memory 20 is a nonvolatile memory that stores data in anonvolatile manner, and an example of this is a NAND flash memory(hereinafter simply referred to as NAND memory). The followingdescription uses an exemplary case where the NAND memory is used as thenonvolatile memory 20. However, the nonvolatile memory 20 can includestorage devices such as a three-dimensional structure flash memory,Resistive Random Access Memory (ReRAM), or Ferroelectric Random AccessMemory (FeRAM), other than the NAND memory. The nonvolatile memory 20need not be a semiconductor memory. The present embodiment can beapplied to various storage media other than the semiconductor memory.

The memory system 1 may be various memory systems including thenonvolatile memory 20, such as a Solid State Drive (SSD) or a memorycard incorporating the memory controller 10 and the nonvolatile memory20 as one package.

The memory controller 10 controls writing to the nonvolatile memory 20in accordance with a write request from the host 30. The memorycontroller 10 controls reading from the nonvolatile memory 20 inaccordance with a read request from the host 30. An example of thememory controller 10 is a semiconductor integrated circuit configured asa System On a Chip (SoC). The memory controller 10 includes a hostinterface (host I/F) 15, a memory interface (memory I/F) 13, a controlunit 11, an encoder/decoder (codec) 14, and a data buffer 12. The hostI/F 15, the memory I/F 13, the control unit 11, the encoder/decoder 14,and the data buffer 12 are interconnected via an internal bus 16. Partor all of the operation of each of components of the memory controller10 described below may be implemented by execution of firmware by acentral processing unit (CPU) or may be implemented by hardware.

The host I/F 15 performs a process according to an interface standardwith respect to the host 30, and outputs a command received from thehost 30, user data to be written, or the like to the internal bus 16.The host I/F 15 transmits user data read from the nonvolatile memory 20and restored, a response from the control unit 11, or the like to thehost 30.

The memory I/F 13 performs writing processing to the nonvolatile memory20 based on an instruction from the control unit 11. Further, the memoryI/F 13 performs reading processing from the nonvolatile memory 20 basedon an instruction from the control unit 11.

The control unit 11 comprehensively controls each of components of thememory system 1. In a case where a command is received from the host 30via the host I/F 15, the control unit 11 performs control according tothe command. For example, the control unit 11 instructs the memory I/F13 to write user data and parity data to the nonvolatile memory 20 inaccordance with a command from the host 30. Further, the control unit 11instructs the memory I/F 13 to read user data and parity data from thenonvolatile memory 20 in accordance with a command from the host 30.

Moreover, in a case where a write request is received from the host 30,the control unit 11 determines a storage region (memory region) on thenonvolatile memory 20 for user data stored in the data buffer 12. Thatis, the control unit 11 manages the writing destination of user data.The correspondence between the logical address of the user data receivedfrom the host 30 and the physical address indicating the storage regionon the nonvolatile memory 20 that stores the user data will be stored asan address conversion table.

Moreover, in a case where a read request is received from the host 30,the control unit 11 converts the logical address designated by the readrequest into a physical address using the above-described addressconversion table, and instructs the memory I/F 13 to perform readingfrom the physical address.

In typical cases, a NAND memory performs writing and reading in dataunits referred to as a page, and performs erasing in data units referredto as a block. In the present embodiment, a plurality of memory cellsconnected to an identical word line is referred to as a memory cellgroup. In a case where the memory cell is a single level cell (SLC), onememory cell group corresponds to one page. In a case where the memorycell is a multiple level cell (MLC), one memory cell group correspondsto a plurality of pages. In the present description, an MLC includes aTriple Level Cell (TLC), and a Quad Level Cell (QLC). Each of memorycells is connected to a word line as well as to a bit line. Therefore,each of memory cells can be identified by an address for identifying aword line and an address for identifying a bit line.

The data buffer 12 temporarily stores user data received by the memorycontroller 10 from the host 30 until the user data is stored in thenonvolatile memory 20. The data buffer 12 temporarily stores the userdata read from the nonvolatile memory 20 until the user data istransmitted to the host 30. The data buffer 12 can be implemented byusing a general-purpose memory such as Static Random Access Memory(SRAM) or Dynamic Random Access Memory (DRAM). The data buffer 12 may bemounted outside of the memory controller 10, rather than being built inthe memory controller 10.

User data transmitted from the host 30 is transferred to the internalbus 16 and temporarily stored in the data buffer 12. The encoder/decoder14 encodes user data stored in the nonvolatile memory 20 to generate acodeword. The encoder/decoder 14 also decodes the received word readfrom the nonvolatile memory 20 and restores user data. Accordingly, theencoder/decoder 14 includes an encoder 17 and a decoder 18. The dataencoded by the encoder/decoder 14 may include control data used insidethe memory controller 10, in addition to user data.

Next, the writing processing according to the present embodiment will bedescribed. The control unit 11 instructs the encoder 17 to encode userdata at writing to the nonvolatile memory 20. At that time, the controlunit 11 determines a storage location (storage address) of the codewordin the nonvolatile memory 20, and instructs the memory I/F 13 about thedetermined storage location.

Based on the instruction from the control unit 11, the encoder 17encodes the user data on the data buffer 12 to generate a codeword.Example of applicable coding methods include a coding method using analgebraic code such as a Bose-Chaudhuri-Hocquenghem (BCH) code and aReed-Solomon (RS) code, and a coding method (product code or the like)using these codes as component codes in the row direction and the columndirection. The memory I/F 13 performs control to store the codeword tothe storage location on the nonvolatile memory 20 instructed by thecontrol unit 11. Hereinafter, a case of using a BCH code that corrects3-bit errors or less will be described as an example.

Next, the processing at the time of reading from the nonvolatile memory20 of the present embodiment will be described. At the time of readingfrom the nonvolatile memory 20, the control unit 11 designates anaddress on the nonvolatile memory 20 and instructs the memory I/F 13 toperform reading. The control unit 11 also instructs the decoder 18 tostart decoding. The memory I/F 13 reads a received word from thedesignated address of the nonvolatile memory 20 in accordance with aninstruction from the control unit 11, and inputs the read received wordto the decoder 18. The decoder 18 decodes the received word read fromthe nonvolatile memory 20.

The decoder 18 decodes the received word read from the nonvolatilememory 20. The decoder 18 is configured such that, when the number ofbit errors (hereinafter, the number of errors) is 2 or 3, calculation ofan inverse element is performed once.

FIG. 2 is a block diagram illustrating a configuration example of thedecoder 18 according to the present embodiment. FIG. 2 illustrates anexample in a case where the decoder 18 is implemented by a hardwarecircuit. As illustrated in FIG. 2 , the decoder 18 includes a syndromecalculation circuit 201, arithmetic circuits 202 to 205, a rootcalculation circuit 100, a root calculation circuit 210, selectioncircuits 220 and 230, an error location calculation circuit 240, and abit flip circuit 250.

The syndrome calculation circuit 201 has a received word r(x) as aninput and calculates and outputs a syndrome. For example, when thereceived word is r(x): =c(x)+e(x), the syndrome calculation circuit 201calculates syndrome s_(i) by s_(i): =r(α^(i)). c(x) represents acodeword, and e(x) represents an error. α represents a primitive elementof GF(2^(m)). When using a BCH code that corrects 3-bit errors or less,the syndrome calculation circuit 201 has the received word r(x) as aninput and outputs syndromes s₁, s₃, and s₅.

The arithmetic circuits 202 to 205 perform the following operationsindividually.

-   -   Arithmetic circuit 202: outputting syndrome s₁ raised to the        power of 3 (an example of power calculation).    -   Arithmetic circuit 203: outputting syndrome s₁ raised to the        power of 5 (an example of power calculation).    -   Arithmetic circuit 204: adding an output value of arithmetic        circuit 202 and syndrome s₃, and outputting β which is a result        of the addition.    -   Arithmetic circuit 205: adding an output value of arithmetic        circuit 203 and syndrome s₅, and outputting γ which is a result        of the addition.

Note that β and γ are examples of values calculated based on thesyndromes. As described below, in the present embodiment and themodification, an inverse element of either β or γ is calculated.

The root calculation circuit 100 calculates the root of the second-orderor third-order error locator polynomial used when the number of errorsis 2 or 3. For example, the root calculation circuit 100 has β and γ asan input, and outputs roots x₁, x₂, and x₃ of the error locatorpolynomial. Details of the root calculation circuit 100 will bedescribed below.

The root calculation circuit 210 calculates a root of a zeroth-order orfirst-order error locator polynomial used when the number of errors is 0or 1. For example, the root calculation circuit 210 has syndrome s₁ asan input, and outputs syndrome s₁ as the root of the error locatorpolynomial.

The number of errors can be estimated as follows using the value of thesyndrome. The number of errors and the value of the syndrome have thefollowing relationships.

-   -   When the number of errors is 0 or 1, s₁ ³=s₃.    -   When the number of errors is 0 or 1, s₁ ⁵=s₅.    -   When the number of errors is 2 or 3, s₁ ³≠s₃.

This relationship can be rephrased as follows.

-   -   When the number of errors is 0 or 1, s₁ ³=s₃ and s₁ ⁵=s₅.    -   When the number of errors is 2 or 3, s₁ ³≠s₃.

Therefore, when (s₁ ³=s₃ or s₁ ⁵≠s₅) and (s₁ ³=s₃) hold, (that is, whens₁ ³=s₃ and s₁ ⁵≠s₅), the number of errors is 4 or more. Assuming thatthe number of errors is 3 or less, the number of errors is 0 or 1 when(s₁ ³=s₃).

Here, when β: =s₁ ³+s₃, and γ: =s₁ ⁵+s₅, β=0 is equivalent to s₁ ³=s₃,and γ=0 is equivalent to s₁ ⁵=s₅. Therefore, when β and γ are used, thefollowing relationship is obtained with respect to the number of errors.

-   -   When (β≠0 or γ≠0) and (β=0) (that is, when β=0 and γ≠0,), the        number of errors is 4 or more.    -   Assuming that the number of errors is 3 or less, when (β=0), the        number of errors is 0 or 1.

The selection circuit 220 selects and outputs either the root outputfrom the root calculation circuit 100 or the root output from the rootcalculation circuit 210 according to the number of errors. As describedabove, for example, β=0 means that the number of errors is 0 or 1.Accordingly, when β=0, the selection circuit 220 selects and outputs theroot output by the root calculation circuit 210.

The selection circuit 230 selects and outputs either the input root orinformation indicating the correction failure according to the number oferrors. As described above, for example, β=0 and γ≠0 means that thenumber of errors is 4 or more. Therefore, when β=0 and γ≠0, theselection circuit 230 outputs information indicating a correctionfailure.

The error location calculation circuit 240 has the root of the errorlocator polynomial as an input and outputs the error location. Forexample, when the roots x₁, x₂, and x₃ output from the root calculationcircuit 100 are input, the error location calculation circuit 240outputs the error locations p₁, p₂, and p₃. When syndrome s₁, which isthe root output from the root calculation circuit 210, is input, theerror location calculation circuit 240 outputs the error location p₁.

The bit flip circuit 250 has the received word r(x) and the errorlocation output from the error location calculation circuit 240 as aninput, and outputs a received word obtained by flipping the bit at theerror location.

Next, details of the root calculation circuit 100 will be described.First, an error locator polynomial will be described.

The lth-order (l is an integer of 0 or more) error locator polynomial isexpressed by the following Formula (1). For example, the error locatorpolynomial when l=0 to 3, that is, the zeroth-order to third-order errorlocator polynomials are expressed by the following Formulas (2) to (5).

$\begin{matrix}{\left\lbrack {{Mathematical}{Formula}1} \right\rbrack} &  \\{\prod_{k = 1}^{l}\left( {x - \alpha^{j_{k}}} \right)} & (1)\end{matrix}$(j_(k):k = 1, 2, …, l − THERRORLOCATION, α : APRIMITIVEEMLEMENTOFGF(2^(m)))$\begin{matrix}{\left\lbrack {{Mathematical}{Formula}2} \right\rbrack} &  \\{{\prod_{k = 1}^{0}\left( {x - \alpha^{j_{k}}} \right)} = 1} & (2)\end{matrix}$ $\begin{matrix}{\left\lbrack {{Mathematical}{Formula}3} \right\rbrack} &  \\{{\prod_{k = 1}^{1}\left( {x - \alpha^{j_{k}}} \right)} = {x + s_{1}}} & (3)\end{matrix}$ $\begin{matrix}{\left\lbrack {{Mathematical}{Formula}4} \right\rbrack} &  \\{{\prod_{k = 1}^{2}\left( {x - \alpha^{j_{k}}} \right)} = {x^{2} + {s_{1}x} + \frac{s_{1}^{3} + s_{3}}{s_{1}}}} & (4)\end{matrix}$ $\begin{matrix}{\left\lbrack {{Mathematical}{Formula}5} \right\rbrack} &  \\{{\prod_{k = 1}^{3}\left( {x - \alpha^{j_{k}}} \right)} = {x^{3} + {s_{1}x^{2}} + {\frac{{s_{1}^{2}s_{3}} + s_{5}}{s_{1}^{3} + s_{3}}x} + \frac{s_{1}^{6} + {s_{1}^{3}s_{3}} + {s_{1}s_{5}} + s_{3}^{2}}{s_{1}^{3} + s_{3}}}} & (5)\end{matrix}$

The root of zeroth-order and first-order error locator polynomials canbe calculated collectively, as described below. Hereinafter, processingof collectively calculating the roots of the zeroth-order andfirst-order error locator polynomials is referred to as root calculationof the zeroth-order and first-order error locator polynomials.Similarly, the root of second-order and third-order error locatorpolynomials can be calculated collectively. Hereinafter, processing ofcollectively calculating the roots of the second-order and third-ordererror locator polynomials is referred to as root calculation of thesecond-order and third-order error locator polynomials.

First, root calculation of a zeroth and first-order error locatorpolynomial will be described. When the number of errors is 0, s₁ ³=s₃and s₁=0 hold, and when the number of errors is 1, s₁ ⁵=s₅ and s₁≠0hold. Therefore, by assuming that σ(x)=x+s₁, and “find the roots of σ(x)and removing 0 from the root of σ(x)”, the root calculation of thezeroth and first-order error locator polynomial can be executed. This isderived from the following.

-   -   When the number of errors is 0, the root of σ(x) is 0, since        s₁=0. Therefore, by removing 0 from the root of σ(x), the root        of the zeroth-order error locator polynomial is determined.    -   When the number of errors is 1, the root of σ(x) is s₁. Here,        s₁≠0 holds, and thus, the root of the first-order error locator        polynomial does not include 0. That is, the root of the        first-order error locator polynomial is not to be removed.        Therefore, by removing 0 from the root of σ(x), the root of the        first-order error locator polynomial is determined.

Next, root calculation of the second and third-order error locatorpolynomial will be described. When the number of errors is 2, s₁ ³≠s₃,s₁ ⁶+s₁s₅=s₁ ³s₃+s₃ ² hold. When the number of errors is 3, s₁ ³≠s₃ ands₁ ⁶+s₁s₅≠s₁ ³s₃+s₃ ² hold. Therefore, by assuming that σ(x) isexpressed by the following Formula (6) and “find the roots of σ(x) andremoving 0 from root of σ(x)”, the root calculation of the second andthird-order error locator polynomial can be executed.

$\begin{matrix}\left\lbrack {{Mathematical}{Formula}6} \right\rbrack &  \\{{\sigma(x)} = {x^{3} + {s_{1}x^{2}} + {\frac{{s_{1}^{2}s_{3}} + s_{5}}{s_{1}^{3} + s_{3}}x} + \frac{s_{1}^{6} + {s_{1}^{3}s_{3}} + {s_{1}s_{5}} + s_{3}^{2}}{s_{1}^{3} + s_{3}}}} & (6)\end{matrix}$

This is derived from the following.

-   -   When the number of errors is 2, the root of σ(x) is the root of        the second-order error locator polynomial and 0 based on the        following Formula (7). Here, (s₁ ³+s₃)/s₁≠0 holds, and thus, the        root of the second-order error locator polynomial does not        include 0. That is, the root of the second-order error locator        polynomial is not to be removed. Therefore, by removing 0 from        the root of σ(x), the root of the second-order error locator        polynomial is determined.    -   When the number of errors is 3, the root of σ(x) is to be the        root of the third-order error locator polynomial. Here, based on        the following Formula (8), the root of the third-order error        locator polynomial does not include 0. That is, the root of the        third-order error locator polynomial is not to be removed.        Therefore, by removing 0 from the root of σ(x), the root of the        third-order error locator polynomial is determined.

$\begin{matrix}\left\lbrack {{Mathematical}{Formula}7} \right\rbrack &  \\{{\sigma(x)} = {{x^{3} + {s_{1}x^{2}} + {\frac{s_{1}^{3} + s_{3}}{s_{1}}x}} = {\left( {x^{2} + {s_{1}x} + \frac{s_{1}^{3} + s_{3}}{s_{1}}} \right)x}}} & (7)\end{matrix}$ $\begin{matrix}\left\lbrack {{Mathematical}{Formula}8} \right\rbrack &  \\{\frac{s_{1}^{6} + {s_{1}^{3}s_{3}} + {s_{1}s_{5}} + s_{3}^{2}}{s_{1}^{3} + s_{3}} \neq 0} & (8)\end{matrix}$

Next, a procedure of root calculation of σ(x) expressed by Formula (6)will be described. When a variable x and a variable y are transformed bythe variable transformation represented by x=y+s₁, then, σ(x) isrepresented by the following Formula (9).

$\begin{matrix}\left\lbrack {{Mathematical}{Formula}9} \right\rbrack &  \\\begin{matrix}{{\sigma(x)} = {\left( {y + s_{1}} \right)^{3} + {s_{1}\left( {y + s_{1}} \right)}^{2} +}} \\{{\frac{{s_{1}^{2}s_{3}} + s_{5}}{s_{1}^{3} + s_{3}}\left( {y + s_{1}} \right)} + \frac{s_{1}^{6} + {s_{1}^{3}s_{3}} + {s_{1}s_{5}} + s_{3}^{2}}{s_{1}^{3} + s_{3}}} \\{= {y^{3} + {\frac{s_{1}^{5} + s_{5}}{s_{1}^{3} + s_{3}}y} + s_{1}^{3} + s_{3}}}\end{matrix} & (9)\end{matrix}$

Formula (9) corresponds to a polynomial obtained by transforming theerror locator polynomial in accordance with the variable transformationof x=y+s₁. Hereinafter, the polynomial obtained by transforming theerror locator polynomial according to the variable transformation inthis manner may be referred to as a transformed polynomial.

Here, let β: =s₁ ³+s₃ and γ: =s₁ ⁵+s₅, then σ(x) is expressed by thefollowing Formula (10). Hereinafter, the case (C1) γ=0 and the case (C2)γ≠0 will be described separately.

$\begin{matrix}\left\lbrack {{Mathematical}{Formula}10} \right\rbrack &  \\{{\sigma(x)} = {y^{3} + {\frac{\gamma}{\beta}y} + \beta}} & (10)\end{matrix}$

Case (C1) γ=0

Based on the following Formula (11), the roots y₁, y₂, and y₃ aredetermined by using correspondence information (such as a lookup table:LUT) that returns the cube root of β by using β as key information. TheLUT is an example of correspondence information in which a plurality ofvalues that can be taken by the key information and the root of thetransformed polynomial are associated with each other, and any otherform of correspondence information may be used.

[Mathematical Formula 11]

σ(x)=y ³+β  (11)

Case (C2) γ≠0

Assuming that the variable y and the variable z are transformed by thevariable transformation expressed by the following Formula (12), rootsz₁, z₂, and z₃ are determined by using the LUT that returns the root ofthe polynomial expressed by the following Formula (14) using γ³/β⁵ askey information based on the following Formula (13).

$\begin{matrix}\left\lbrack {{Mathematical}{Formula}12} \right\rbrack &  \\{y = {\sqrt{\frac{\gamma}{\beta}}z}} & (12)\end{matrix}$ $\begin{matrix}\left\lbrack {{Mathematical}{Formula}13} \right\rbrack &  \\{{\sigma(x)} = {{\left( {\sqrt{\frac{\gamma}{\beta}}z} \right)^{3} + {\frac{\gamma}{\beta}\left( {\sqrt{\frac{\gamma}{\beta}}z} \right)} + \beta} = {\left( \sqrt{\frac{\gamma}{\beta}} \right)^{3}\left( {z^{3} + z + \sqrt{\frac{\beta^{5}}{\gamma^{3}}}} \right)}}} & (13)\end{matrix}$ $\begin{matrix}\left\lbrack {{Mathematical}{Formula}14} \right\rbrack &  \\{z^{3} + z + \sqrt{\frac{\beta^{5}}{\gamma^{3}}}} & (14)\end{matrix}$

Furthermore, by multiplying each of the obtained roots z₁, z₂, and z₃ by√(γ/β), it is possible to determine roots y₁, y₂, and y₃ of σ(x). Notethat “√( )” represents the square root (squared root) of the value inparentheses. Furthermore, by adding s₁ to each of the obtained roots y₁,y₂, and y₃, it is possible to determine roots x₁, x₂, and x₃ of σ(x).

Note that the cube root y₂ and y₃ of β may be determined by y₂=y₁ω andy₃=y₁ω² using the cube root y₁ of β, where ω is the cube root of 1.

Alternatively, the root x₃ of σ(x) may be determined by x₃=x₁+x₂+s₁using the roots x₁ and x₂ of σ(x). In this case, it is only necessary todetermine the roots y₁ and y₂ and the roots z₁ and z₂.

It is conceivable to use a method of obtaining the root of Formula (14),which is a method using a LUT with √(β⁵/γ³) included in the Formula (14)itself as key information. Hereinafter, a comparative example configuredas described above will be described. In the comparative example, whenγ≠0, the roots z₁, z₂, and z₃ are determined by using √(β⁵/γ³) as keyinformation and using a LUT that returns the root of the polynomialexpressed by Formula (14). The subsequent processing of determining theroots y₁, y₂, and y₃ from the roots z₁, z₂, and z₃ and the processing ofdetermining the roots x₁, x₂, and x₃ from the roots y₁, y₂, and y₃ aresimilar to the processing of the present embodiment.

The comparative example needs calculation of the following two inverseelements.

-   -   1/γ used to calculate the key information √(β⁵/γ³).    -   1/β used to calculate √(γ/β) to be multiplied by the roots z₁,        z₂, and z₃ when determining the roots y₁, y₂, and y₃.

In contrast, the present embodiment does not use a LUT having acoefficient √(β⁵/γ³) itself included in Formula (14) but uses a LUThaving γ³/β⁵ as key information. In other words, the present embodimentuses γ³/β⁵, which is key information that uniquely determines thecoefficient √(β⁵/γ³) included in Formula (14). With this operation, thepresent embodiment is only necessary to perform the followingcalculation of one inverse element.

-   -   1/β used to calculate the key information γ³/β⁵ and √(γ/β).

In other words, in the present embodiment, the variable transformation(for example, Formula (12)) and the calculation of the root of thetransformed polynomial (for example, Formula (13)) can be executed usingone inverse element calculation.

The present embodiment can be interpreted that a LUT that returns theroot of the polynomial expressed by the following Formula (15) is to beused in a case where the input is c. In contrast, the comparativeexample can be interpreted that a LUT that returns the root of thepolynomial z³+z+c is to be used when the input is c.

$\begin{matrix}\left\lbrack {{Mathematical}{Formula}15} \right\rbrack &  \\{z^{3} + z + \sqrt{\frac{1}{c}}} & (15)\end{matrix}$

In this manner, by changing the key information used in the LUT, theinverse element calculation can be reduced from twice to once in thepresent embodiment.

The root calculation circuit 100 is configured to execute rootcalculation of the second and third-order error locator polynomial asdescribed above. Details of the root calculation circuit 100 of FIG. 2will be described. The root calculation circuit 100 includes rootcalculation circuits 110 and 120, a selection circuit 131, andarithmetic circuits 132 to 135.

The root calculation circuit 110 calculates the root at the case (C1)γ=0. The root calculation circuit 110 includes a LUT 111 and anarithmetic circuit 112. The LUT 111 and the arithmetic circuit 112execute the following operations individually.

-   -   LUT 111: outputting a root y₁ which is the cube root of β.    -   Arithmetic circuit 112: multiplying the root y₁ by ω (cube root        of 1) to output root y₂ as a result of the multiplication.

The root calculation circuit 120 performs the root calculation for thecase (C2) γ≠0. The root calculation circuit 120 includes arithmeticcircuits 121 to 126, a LUT 127, and arithmetic circuits 128 and 129. Thearithmetic circuit 121 to 126, the LUT 127, and the arithmetic circuits128 and 129 execute the following operations, individually.

-   -   Arithmetic circuit 121: calculating an inverse element 1/β of β        (inverse element calculation circuit).    -   Arithmetic circuit 122: multiplying inverse element 1/β and γ,        and outputting γ/β which is a result of the multiplication.    -   Arithmetic circuit 123: calculating γ³ which is a cube of γ (an        example of power calculation).    -   Arithmetic circuit 124: calculating 1/β⁵, which is the 5th power        of the inverse element 1/β (an example of power calculation).    -   Arithmetic circuit 125: calculating square root √(γ/β) of γ/β.    -   Arithmetic circuit 126: multiplying γ³ and 1/β⁵, and outputting        γ³/β⁵ which is a result of the multiplication.    -   LUT 127 outputting roots z₁ and z₂ with γ³/β⁵ as key        information.    -   Arithmetic circuit 128: multiplying root z₁ by √(γ/β), and        outputting root y₁ as a result of the multiplication.    -   Arithmetic circuit 129: multiplying root z₂ by √(γ/β), and        outputting root y₂ as a result of the multiplication.

Depending on whether γ is 0, the selection circuit 131 selects andoutputs either: the roots y₁ and y₂ calculated by the root calculationcircuit 110; or the roots y₁ and y₂ calculated by the root calculationcircuit 120.

The arithmetic circuit 132 to 135 performs the following operationsindividually.

-   -   Arithmetic circuit 132: adding syndrome s₁ to root y₁, and        outputting root x₁ as a result of the addition.    -   Arithmetic circuit 133: adding syndrome s₁ to root y₂, and        outputting root x₂ as a result of the addition.    -   Arithmetic circuit 134: adding root x₂ to root x₁, and        outputting x₁+x₂ as a result of the addition.    -   Arithmetic circuit 135: adding syndrome s₁ to x₁+x₂, and        outputting root x₃ as a result of the addition.

The arithmetic operations by the arithmetic circuits 132 to 135 can beinterpreted as arithmetic operations of executing inverse transformationof variable transformation (variable inverse transformation) on theroots y₁ and y₂ of the transformed polynomial to determine the roots x₁,x₂, and x₃ of the error locator polynomial.

Here, a configuration example of a circuit of a comparative example willbe described. FIG. 3 is a diagram illustrating a configuration exampleof a circuit of the comparative example. In the comparative example, theconfiguration of the root calculation circuit 120 is different from theconfiguration of the present embodiment. Therefore, FIG. 3 mainlyillustrates a root calculation circuit 60 of the comparative examplecorresponding to the root calculation circuit 120. Hereinafter, the rootcalculation circuit 60 will be described. The same components as thosein FIG. 2 are denoted by the same reference numerals, and thedescription thereof will be omitted.

The root calculation circuit 60 includes arithmetic circuits 61 to 65, aLUT 66, and arithmetic circuits 121, 122, 125, 128, and 129. Thearithmetic circuit 61 to 65 and the LUT 66 perform the followingoperations individually.

-   -   Arithmetic circuit 61: calculating inverse element 1/γ of γ        (inverse element calculation circuit).    -   Arithmetic circuit 62: calculating 1/γ³ which is the cube of        inverse element 1/γ.    -   Arithmetic circuit 63: calculating β⁵ which is the 5th power of        β.    -   Arithmetic circuit 64: multiplying 1/γ³ and β⁵, and outputting        β⁵/γ³ which is a result of the multiplication.    -   Arithmetic circuit 65: calculating square root √(β⁵/γ³) of        β⁵/γ³.    -   LUT 66: Outputting roots z₁ and z₂ using √(β⁵/γ³) as key        information.

In this manner, in the comparative example, two arithmetic circuits 61and 121 are required as inverse element calculation circuits. Incontrast, the present embodiment only needs to have one inverse elementcalculation circuit (arithmetic circuit 121). The inverse elementcalculation circuit can be larger in circuit scale than other arithmeticcircuits. Even in such a case, the number of inverse element calculationcircuits can be reduced according to the present embodiment, making ispossible to further efficiently reduce the circuit scale of the decoder18.

In a case where the decoder 18 is implemented by a CPU and firmware, thefirmware can be configured to execute one inverse element calculationfor root calculation of a second and third-order error locatorpolynomial. That is, firmware for executing error correction (decoding)can be formed with a simpler configuration.

Next, a flow of decoding processing by the memory system 1 will bedescribed. FIG. 4 is a flowchart illustrating an example of decodingprocessing according to the present embodiment.

The control unit 11 reads the error correcting code from the nonvolatilememory 20, and obtains a received word (Step S101). The control unit 11also instructs the decoder 18 to start decoding.

The syndrome calculation circuit 201 of the decoder 18 calculates asyndrome from the received word (Step S102).

Next, the decoder 18 estimates the number of errors (Step S103). Thedecoder 18 judges whether the number of errors is 3 or less (Step S104).In a case where the number of errors is larger than 3 (Step S104: No),the decoder 18 provides notification of a decoding failure (Step S110),and ends the decoding processing.

When the number of errors is 3 or less (Step S104: Yes), the decoder 18further judges whether the number of errors is 1 or less (Step S105). Ina case where the number of errors is 1 or less (Step S105: Yes), thedecoder 18 executes root calculation of a zeroth and first-order errorlocator polynomial (Step S106). When the number of errors is not 1 orless (Step S105: No), the decoder 18 executes root calculation of thesecond and third-order error locator polynomial (Step S107).

When having executed the root calculation of the second and third-ordererror locator polynomial, the decoder 18 judges whether the root hasbeen obtained by the root calculation of the second and third-ordererror locator polynomial (Step S108).

For the second and third-order error locator polynomials, there is acase where no root exists for the value of γ³/β⁵. In such a case, forexample, the LUT is constructed to associate information indicatingabsence of root with the key information of the LUT corresponding tothis value. When the information indicating that the absence of root isobtained from the LUT, the decoder 18 judges that the root cannot beobtained. Note that syndrome s₁ is always obtained as a root for thezeroth and first-order error locator polynomial.

When the root has not been obtained (Step S108: No), the decoder 18provides notification of a decoding failure (Step S110), and ends thedecoding processing.

When the root has been obtained (Step S108: Yes), and after the rootcalculation of the zeroth and first-order error locator polynomial, thedecoder 18 corrects the error of the error location corresponding to theroot (Step S109), and ends the decoding processing.

The decoder 18 may judge whether the values of all the syndromes are 0after calculating the syndromes in Step S102, for example, and may endthe decoding processing when all the syndromes are 0. This is becausewhen all syndromes are 0, it can be determined that there is no error inthe received word.

Although the above has described a case of using the BCH code thatcorrects 3-bit errors or less as an example, the similar procedure canalso be applied to a configuration using a BCH code that corrects n-biterrors (n is an integer of 3 or more) or less. For example, in a case ofusing a BCH code for correcting 5-bit errors or less, the aboveprocedure can be applied to decoding in a case where the number oferrors is 0 to 3. Any procedure may be used for decoding in a case wherethe number of errors is 4 or 5.

The calculation of the root at γ≠0 is not limited to the above, and maybe configured as the following modifications. Hereinafter, amodification in which variable transformation different from theabove-described embodiment is performed will be described. Each variabletransformation is a transformation in which the root of the transformedpolynomial obtained by transforming the error locator polynomialaccording to the variable transformation is determined for one piece ofkey information. Variable transformation different from the followingmodification may be used as long as the transformation is performed inthis manner.

In each modification, the procedure of the root calculation of thesecond and third-order error locator polynomial (the configuration ofthe root calculation circuit 120) is different from the configuration ofthe above embodiment, while other functions are similar to those of theabove embodiment. Therefore, details of the root calculation circuit ofeach modification will be described below. In the root calculationcircuit of each modification, an internal arithmetic circuit or the likecan have a function similar to the function of the above embodiment.Such a configuration is denoted by the same reference numeral as that ofthe above-described embodiment, and description thereof is omitted.

(First Modification)

Root calculation of the second and third-order error locator polynomialin the first modification will be described. In the presentmodification, here is an assumable case where the variable y and thevariable z are transformed by the variable transformation expressed bythe following Formula (16). In this case, by using a LUT that returns avalue obtained by adding 1 to the roots z₁, z₂, and z₃ of the polynomialexpressed by Formula (18) with γ³/β⁵ as key information based on thefollowing Formula (17), z₁+1, z₂+1, and z₃+1 are each determined.

$\begin{matrix}{\left\lbrack {{Mathematical}{Formula}16} \right\rbrack} &  \\{y = {\sqrt{\frac{\gamma}{\beta}}\left( {z + 1} \right)}} & (16)\end{matrix}$ $\begin{matrix}{\left\lbrack {{Mathematical}{Formula}17} \right\rbrack} &  \\{{\sigma(x)} = {{\left( {\sqrt{\frac{\gamma}{\beta}}\left( {z + 1} \right)} \right)^{3} + {\frac{\gamma}{\beta}\left( {\sqrt{\frac{\gamma}{\beta}}\left( {z + 1} \right)} \right)} + \beta} = {\left( \sqrt{\frac{\gamma}{\beta}} \right)^{3}\left( {z^{3} + z^{2} + \sqrt{\frac{\beta^{5}}{\gamma^{3}}}} \right)}}} & (17)\end{matrix}$ $\begin{matrix}{\left\lbrack {{Mathematical}{Formula}18} \right\rbrack} &  \\{z^{3} + z^{2} + \sqrt{\frac{\beta^{5}}{\gamma^{3}}}} & (18)\end{matrix}$

Furthermore, by multiplying each of obtained values z₁+1, z₂+1, and z₃+1by √(γ/β), it is possible to determine roots y₁, y₂, and y₃ of σ(x).Furthermore, by adding s₁ to each of the obtained roots y₁, y₂, and y₃,it is possible to determine roots x₁, x₂, and x₃ of σ(x).

The present modification can be interpreted that a LUT that returns avalue obtained by adding 1 to the root of the polynomial expressed byFormula (19) is used in a case where the input is c.

$\begin{matrix}\left\lbrack {{Mathematical}{Formula}19} \right\rbrack &  \\{z^{3} + z^{2} + \sqrt{\frac{1}{c}}} & (19)\end{matrix}$

FIG. 5 is a diagram illustrating a configuration example of a rootcalculation circuit 120-2 of the present modification. As illustrated inFIG. 5 , the root calculation circuit 120-2 includes arithmetic circuits121 to 126, a LUT 127-2, and arithmetic circuits 128 and 129. In thepresent modification, the configuration of the LUT 127-2 is differentfrom the configuration of the above embodiment.

The LUT 127-2 outputs values z₁+1 and z₂+1 obtained by adding 1 to theroots z₁ and z₂ with γ³/β⁵ as key information. Although there is adifference in values to be input to the arithmetic circuits 128 and 129,the arithmetic operations (multiplication) to be executed are similar tothe case of the above embodiment. For example, the arithmetic circuits128 and 129 is only required to perform multiplication using values z₁+1and z₂+1 instead of the roots z₁ and z₂, respectively.

(Second Modification)

Root calculation of the second and third-order error locator polynomialin a second modification will be described. In the present modification,assuming that the variable y and the variable z are transformed by thevariable transformation expressed by the following Formula (20), z₁, z₂,and z₃ are determined by using the LUT that returns the root of thepolynomial expressed by Formula (22) with β⁵/γ³ as key information basedon the following Formula (21).

$\begin{matrix}\left\lbrack {{Mathematical}{Formula}20} \right\rbrack &  \\{y = {\frac{\beta^{2}}{\gamma}z}} & (20)\end{matrix}$ $\begin{matrix}\left\lbrack {{Mathematical}{Formula}21} \right\rbrack &  \\{{\sigma(x)} = {{\left( {\frac{\beta^{2}}{\gamma}z} \right)^{3} + {\frac{\gamma}{\beta}\left( {\frac{\beta^{2}}{\gamma}z} \right)} + \beta} = {\left( \frac{\beta^{2}}{\gamma} \right)^{3}\left( {z^{3} + {\frac{\gamma^{3}}{\beta^{5}}z} + \frac{\gamma^{3}}{\beta^{5}}} \right)}}} & (21)\end{matrix}$ $\begin{matrix}\left\lbrack {{Mathematical}{Formula}22} \right\rbrack &  \\{z^{3} + {\frac{\gamma^{3}}{\beta^{5}}z} + \frac{\gamma^{3}}{\beta^{5}}} & (22)\end{matrix}$

In addition, by multiplying each of the obtained values z₁, z₂, and z₃by β²/γ, it is possible to determine roots y₁, y₂, and y₃ of σ(x).Furthermore, by adding s₁ to each of the obtained roots y₁, y₂, and y₃,it is possible to determine roots x₁, x₂, and x₃ of σ(x).

The present modification can be interpreted that a LUT that returns theroot of the polynomial expressed by Formula (23) is used in a case wherethe input is c.

$\begin{matrix}\left\lbrack {{Mathematical}{Formula}23} \right\rbrack &  \\{z^{3} + {\frac{1}{c}z} + \frac{1}{c}} & (23)\end{matrix}$

FIG. 6 is a diagram illustrating a configuration example of a rootcalculation circuit 120-3 of the present modification. As illustrated inFIG. 6 , the root calculation circuit 120-3 includes arithmetic circuits121-3 a, 121-3 b, 122 to 124, and 126, a LUT 127-3, and arithmeticcircuits 128 and 129. The present modification is different from theabove embodiment in the configuration of the LUT 127-3 and thatarithmetic circuits 121-3 and 125-3 are provided instead of thearithmetic circuits 121 and 125 respectively.

The arithmetic circuits 121-3 and 125-3 perform the following operationsindividually.

-   -   Arithmetic circuit 121-3: calculating an inverse element 1/γ of        γ (inverse element calculation circuit).    -   Arithmetic circuit 125-3: calculating β² which is the square of        β.

The LUT 127-3 outputs the roots z₁ and z₂ with β⁵/γ³ as key information.Although there is a difference in values to be input to the arithmeticcircuits 122-124, 126, 128 and 129, the arithmetic operations to beexecuted are similar to the case of the above embodiment.

(Third Modification)

In the third modification, here is an assumable case where the variabley and the variable z are transformed by the variable transformationexpressed by the following Formula (24). In this case, by using a LUTthat returns a value obtained by adding 1 to the roots of the polynomialexpressed by Formula (26) with β⁵/γ³ as key information based on thefollowing Formula (25), z₁+1, z₂+1, and z₃+1 are each determined.

$\begin{matrix}{\left\lbrack {{Mathematical}{Formula}24} \right\rbrack} &  \\{y = {\frac{\beta^{2}}{\gamma}\left( {z + 1} \right)}} & (24)\end{matrix}$ $\begin{matrix}{\left\lbrack {{Mathematical}{Formula}25} \right\rbrack} &  \\{{\sigma(x)} = {{\left( {\frac{\beta^{2}}{\gamma}\left( {z + 1} \right)} \right)^{3} + {\frac{\gamma}{\beta}\left( {\frac{\beta^{2}}{\gamma}\left( {z + 1} \right)} \right)} + \beta} = {\left( \frac{\beta^{2}}{\gamma} \right)^{3}\left( {z^{3} + z^{2} + {\left( {1 + \frac{\gamma^{3}}{\beta^{5}}} \right)z} + 1} \right)}}} & (25)\end{matrix}$ $\begin{matrix}{\left\lbrack {{Mathematical}{Formula}26} \right\rbrack} &  \\{z^{3} + z^{2} + {\left( {1 + \frac{\gamma^{3}}{\beta^{5}}} \right)z} + 1} & (26)\end{matrix}$

Furthermore, by multiplying each of obtained values z₁+1, z₂+1, and z₃+1by β²/γ, it is possible to determine roots y₁, y₂, and y₃ of σ(x).Furthermore, by adding s₁ to each of the obtained roots y₁, y₂, and y₃,it is possible to determine roots x₁, x₂, and x₃ of σ(x).

The present modification can be interpreted that a LUT that returns avalue obtained by adding 1 to the root of the polynomial expressed byFormula (27) is used in a case where the input is c.

$\begin{matrix}\left\lbrack {{Mathematical}{Formula}27} \right\rbrack &  \\{z^{3} + z^{2} + {\left( {1 + \frac{1}{c}} \right)z} + 1} & (27)\end{matrix}$

FIG. 7 is a diagram illustrating a configuration example of a rootcalculation circuit 120-4 of the present modification. As illustrated inFIG. 7 , the root calculation circuit 120-3 includes arithmetic circuits121-3122 to 124, 125-3, and 126, a LUT 127-4, and arithmetic circuits128 and 129. In the present modification, the configuration of the LUT127-3 is different from the configuration of the third modification.

The LUT 127-4 outputs values z₁+1 and z₂+1 obtained by respectivelyadding 1 to the roots z₁ and z₂, with β⁵/γ³ as key information. Althoughthere is a difference in values to be input to the arithmetic circuits128 and 129, the arithmetic operations to be executed are similar to thecase of the third modification.

As described above, according to the present embodiment, errorcorrection (decoding) can be executed with a simpler configuration.

What is claimed is:
 1. A memory system comprising: a nonvolatile memorythat stores data encoded with an error correcting code for correctingn-bit errors or less, n being an integer of 3 or more; and a memorycontroller that: reads a received word from the nonvolatile memory;calculates a syndrome using the read received word; estimates the numberof bit errors using the syndrome; calculates an inverse element of avalue calculated based on the syndrome in a case where the number of biterrors is 2 or 3; executes, by using the inverse element, variabletransformation on a variable of an error locator polynomialcorresponding to the number of bit errors and calculation of a root of atransformed polynomial obtained by transforming the error locatorpolynomial according to the variable transformation; executes variableinverse transformation on a root of the transformed polynomial to obtaina root of the error locator polynomial; and corrects an error of anerror location corresponding to the root of the error locatorpolynomial.
 2. The memory system according to claim 1, wherein, when thenumber of bit errors is 2 or 3, the memory controller calculates theinverse element, calculates key information by at least one ofmultiplication and power calculation on the inverse element, anddetermining the root corresponding to the calculated key information byusing correspondence information in which a plurality of values that canbe taken by the key information and the root of the transformedpolynomial are associated with each other.
 3. The memory systemaccording to claim 2, wherein the memory controller calculates the keyinformation uniquely determined from a coefficient calculated by usingthe inverse element among coefficients included in the transformedpolynomial.
 4. The memory system according to claim 3, wherein thevariable transformation is a transformation in which the root of thetransformed polynomial is determined for one piece of the keyinformation.
 5. The memory system according to claim 2, wherein thememory controller executes, when the key information is represented byγ³/β⁵, the variable transformation represented by Formula (1) and thecalculation of the root of the transformed polynomial represented byFormula (2). $\begin{matrix}\left\lbrack {{Mathematical}{Formula}1} \right\rbrack &  \\{{x = {y + s_{1}}},{y = {\sqrt{\frac{\gamma}{\beta}}z}}} & (1)\end{matrix}$ $\begin{matrix}\left\lbrack {{Mathematical}{Formula}2} \right\rbrack &  \\{z^{3} + z + \sqrt{\frac{\beta^{5}}{\gamma^{3}}}} & (2)\end{matrix}$
 6. The memory system according to claim 2, wherein thememory controller executes, when the key information is represented byγ³/β⁵, the variable transformation represented by Formula (3) and thecalculation of the root of the transformed polynomial represented byFormula (4). $\begin{matrix}\left\lbrack {{Mathematical}{Formula}3} \right\rbrack &  \\{{x = {y + s_{1}}},{y = {\sqrt{\frac{\gamma}{\beta}}\left( {z + 1} \right)}}} & (3)\end{matrix}$ $\begin{matrix}\left\lbrack {{Mathematical}{Formula}4} \right\rbrack &  \\{z^{3} + z^{2} + \sqrt{\frac{\beta^{5}}{\gamma^{3}}}} & (4)\end{matrix}$
 7. The memory system according to claim 2, wherein thememory controller executes, when the key information is represented byβ⁵/γ³, the variable transformation represented by Formula (5) and thecalculation of the root of the transformed polynomial represented byFormula (6). $\begin{matrix}\left\lbrack {{Mathematical}{Formula}5} \right\rbrack &  \\{{x = {y + s_{1}}},{y = {\frac{\beta^{2}}{\gamma}z}}} & (5)\end{matrix}$ $\begin{matrix}\left\lbrack {{Mathematical}{Formula}6} \right\rbrack &  \\{z^{3} + {\frac{\gamma^{3}}{\beta^{5}}z} + \frac{\gamma^{3}}{\beta^{5}}} & (6)\end{matrix}$
 8. The memory system according to claim 2, wherein thememory controller executes, when the key information is represented byβ⁵/γ³, the variable transformation represented by Formula (7) and thecalculation of the root of the transformed polynomial represented byFormula (8). $\begin{matrix}\left\lbrack {{Mathematical}{Formula}7} \right\rbrack &  \\{{x = {y + s_{1}}},{y = {\frac{\beta^{2}}{\gamma}\left( {z + 1} \right)}}} & (7)\end{matrix}$ $\begin{matrix}\left\lbrack {{Mathematical}{Formula}8} \right\rbrack &  \\{z^{3} + z^{2} + {\left( {1 + \frac{\gamma^{3}}{\beta^{5}}} \right)z} + 1} & (8)\end{matrix}$
 9. The memory system according to claim 2, wherein thememory controller executes, when the key information is represented byβ, the variable transformation represented by Formula (9) and thecalculation of the root of the transformed polynomial represented byFormula (10).[Mathematical Formula 9]x=y+s ₁   (9)[Mathematical Formula 10]y³+β  (10)
 10. The memory system according to claim 1, wherein thememory controller includes one inverse element calculation circuit thatcalculates the inverse element in a case where the number of bit errorsis 2 or
 3. 11. A method of controlling a nonvolatile memory, the methodcomprising: storing, in the nonvolatile memory, data encoded with anerror correcting code for correcting n-bit errors or less, n being aninteger of 3 or more; reading a received word from the nonvolatilememory; calculating a syndrome using the read received word; estimatingthe number of bit errors using the syndrome; calculating an inverseelement of a value calculated based on the syndrome in a case where thenumber of bit errors is 2 or 3; executing, by using the inverse element,variable transformation on a variable of an error locator polynomialcorresponding to the number of bit errors and calculation of a root of atransformed polynomial obtained by transforming the error locatorpolynomial according to the variable transformation; executing variableinverse transformation on a root of the transformed polynomial to obtaina root of the error locator polynomial; and correcting an error of anerror location corresponding to the root of the error locatorpolynomial.
 12. The method according to claim 11, wherein, when thenumber of bit errors is 2 or 3, the inverse element is calculated, keyinformation is calculated by at least one of multiplication and powercalculation on the inverse element, and the root corresponding to thecalculated key information is determined by using correspondenceinformation in which a plurality of values that can be taken by the keyinformation and the root of the transformed polynomial are associatedwith each other.
 13. The method according to claim 12, wherein the keyinformation uniquely determined from a coefficient calculated by usingthe inverse element among coefficients included in the transformedpolynomial is calculated.
 14. The method according to claim 13, whereinthe variable transformation is a transformation in which the root of thetransformed polynomial is determined for one piece of the keyinformation.
 15. The method according to claim 12, wherein, when the keyinformation is represented by γ³/β⁵, the variable transformationrepresented by Formula (1) and the calculation of the root of thetransformed polynomial represented by Formula (2) are executed.$\begin{matrix}\left\lbrack {{Mathematical}{Formula}1} \right\rbrack &  \\{{x = {y + s_{1}}},{y = {\sqrt{\frac{\gamma}{\beta}}z}}} & (1)\end{matrix}$ $\begin{matrix}\left\lbrack {{Mathematical}{Formula}2} \right\rbrack &  \\{z^{3} + z + \sqrt{\frac{\beta^{5}}{\gamma^{3}}}} & (2)\end{matrix}$
 16. The method according to claim 12, wherein, when thekey information is represented by γ³/β⁵, the variable transformationrepresented by Formula (3) and the calculation of the root of thetransformed polynomial represented by Formula (4) are executed.$\begin{matrix}\left\lbrack {{Mathematical}{Formula}3} \right\rbrack &  \\{{x = {y + s_{1}}},{y = {\sqrt{\frac{\gamma}{\beta}}\left( {z + 1} \right)}}} & (3)\end{matrix}$ $\begin{matrix}\left\lbrack {{Mathematical}{Formula}4} \right\rbrack &  \\{z^{3} + z^{2} + \sqrt{\frac{\beta^{5}}{\gamma^{3}}}} & (4)\end{matrix}$
 17. The method according to claim 12, wherein, when thekey information is represented by β⁵/γ³, the variable transformationrepresented by Formula (5) and the calculation of the root of thetransformed polynomial represented by Formula (6) are executed.$\begin{matrix}\left\lbrack {{Mathematical}{Formula}5} \right\rbrack &  \\{{x = {y + s_{1}}},{y = {\frac{\beta^{2}}{\gamma}z}}} & (5)\end{matrix}$ $\begin{matrix}\left\lbrack {{Mathematical}{Formula}6} \right\rbrack &  \\{z^{3} + {\frac{\gamma^{3}}{\beta^{5}}z} + \frac{\gamma^{3}}{\beta^{5}}} & (6)\end{matrix}$
 18. The method according to claim 12, wherein, when thekey information is represented by β⁵/γ³, the variable transformationrepresented by Formula (7) and the calculation of the root of thetransformed polynomial represented by Formula (8) are executed.$\begin{matrix}\left\lbrack {{Mathematical}{Formula}7} \right\rbrack &  \\{{x = {y + s_{1}}},{y = {\frac{\beta^{2}}{\gamma}\left( {z + 1} \right)}}} & (7)\end{matrix}$ $\begin{matrix}\left\lbrack {{Mathematical}{Formula}8} \right\rbrack &  \\{z^{3} + z^{2} + {\left( {1 + \frac{\gamma^{3}}{\beta^{5}}} \right)z} + 1} & (8)\end{matrix}$
 19. The method according to claim 12, wherein, when thekey information is represented by β, the variable transformationrepresented by Formula (9) and the calculation of the root of thetransformed polynomial represented by Formula (10) are executed.[Mathematical Formula 9]x=y+s ₁   (9)[Mathematical Formula 10]y³+β  (10)